1. Field of the Invention
The present invention relates in general to clock signal generators and in particular to a triggered clock signal producing an output signal with an accurately adjustable delay following assertion of a trigger signal.
2. Description of Related Art
Several test instruments may be used concurrently when testing an integrated circuit device under test (DUT). For example a waveform generator may stimulate one terminal of a DUT with a test signal while a digitizer digitizes a resulting DUT output signal appearing at another DUT terminal. In a coherent test system operations of synchronous test instruments are synchronized to a master clock signal.
FIG. 1 illustrates a typical prior art coherent test system employing two test instruments 1 and 2 for carrying out a test on a DUT 3. A period generator 4 provides a clock signal (CLOCKA) as a timing reference to test instrument 1 while another period generator 5 provides another clock signal (CLOCKB) as a timing reference to test instrument 2. The CLOCKA and CLOCKB signals are coherent because they use the same master clock signal (MCLOCK) as a timing reference. Before the start of the test, gates 6 and 7 prevent the MCLOCK signal from reaching period generators 4 and 5 to keep the CLOCKA and CLOCKB signals turned off. A TRIGGER signal, asserted at the start of the test, arms gates 6 and 7 and the leading edge of the next MCLOCK signal pulse enables gates 6 and 7 thereby allowing them to begin delivering the MCLOCK signal to the period generators 4 and 5. Since period generators 4 and 5 begin producing their respective clock signals at the same time, test instruments 1 and 2 begin their test activities concurrently and conduct those activities synchronously thereafter.
In the clock distribution system of FIG. 1 period generators 4 and 5 don't directly start their output CLOCKA and CLOCKB signal streams in response to assertion of the TRIGGER signal but in response to the first MCLOCK signal pulse to arrive after the TRIGGER signal. When the TRIGGER signal happens to arrive at gates 6 and 7 substantially coincident with an edge of an MCLOCK signal pulse, that MCLOCK signal pulse may enable only one of the gates. The other gate may not be enabled until the arrival of the next MCLOCK signal pulse. This can happen when the TRIGGER or MCLOCK signal arrives at the gates 6 and 7 at slightly different times or if gates 6 and 7 have slightly different triggering levels. In such case the CLOCKA and CLOCKB signals will be out of synchronization by a full MCLOCK period. What is needed is a method for resolving this problem.